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Demo

These are real working demos which you will find in the installation 'demo' directory. These are written in python, but perl functionality is the same. There are some older simpler perl demos here.

Search Application - Showing how all nets and registers in the design can be accessed.

Driver Application - Showing a basic bus controller.

Slave Application - Showing a typical memory.

Monitor Application - Displays simulation activity in a Tk window.

Demo.v - Verilog code using all programs.

Resulting Display using this verilog and these scripts.

Search Application

#
# Here is a demo of ScriptSim's ability to search a design
#

# Lets print out all registers and nets in the design

from ss_lib import * # import the scriptsim library functions

sim = scriptsim.Simulator()
display = scriptsim.Display()

# here is the library object for higher level functions
slib = SS(sim, display)

for i in slib.find(slib.module_list('/'), ["accRegister","accNet"]):
vvo = sim.vvo(i.fullname)
print i.fullname,"in file",i.filename,"line",i.lineno,"has type",i.acctype,"and value",str(vvo)

The result of this program is a listing such as:

Demopy.clock in file demopy.v line 3 has type accNet and value 0bx
Demopy.clock_reg in file demopy.v line 8 has type accRegister and value 0b1
Demopy.test_integer in file demopy.v line 22 has type accIntegerVar and value 0b101
Demopy.test_real in file demopy.v line 24 has type accRealVar and value 5.7

Driver Application

# Here is a simple application which generates read and write commands
# on a simple bus. The verilog nets consist of a clock signal
# called 'clk', a 2-bit control bus called 'control' which indicates
# read and write operations, an address bus, and a data bus.

# Here it is assumed that the verilog code generates the clock and
# also has a memory. As a demo, a separate perl or python program
# implements the memory.

# You need to add the following line to your verilog code,
# specifying the name of the program to run and the names
# of the verilog nets.

# $scriptsim("master.py", clk, control, address, data);

# Now lets create a program which drives the control, address,
# and (for writes) data. You implicitly use the ScriptSim module which
# provides all the interfaces to the simulator and display:

import whrandom # python module for random number generation

# the sim object's methods allow access to the simulator

sim = scriptsim.Simulator()

# give names to the $scriptsim() arguments
clk, cmd, adr, data_in, data_out = sim.argv[1:]

# setup to do everything on the rising clock edge
clk.setup_event(scriptsim.RISING)

# lets make some defines
OP_IDLE, OP_WRITE, OP_READ, OP_DATA = range(4)

#
# initialize all outputs
#
op = OP_IDLE # remember the previous operation.
cmd.v = op # start out driving IDLE as the cmd bus command
adr.v = 0
data_out.v = 'z' # sets all data bits to 'z'

#
# infinite loop creating operations
#
print '\n This is the bus master, master.py\n'
while 1:
    sim.resume_and_wait_for_event()
    if sim.time() < 10: # don't start anything too soon
        continue
    if op == OP_READ: # previous operation was read, so now comes read data
        op = OP_DATA
    else:
        op = whrandom.randint(OP_IDLE, OP_READ)# get a random operation
    cmd.v = op
    if op == OP_WRITE:
        data_out.v = whrandom.randint(0,0xffff)# drive some random data
    else:
        data_out.v = 'z'
    if op == OP_WRITE or op == OP_READ: # if read or write, compute some address
        adr.v = whrandom.randint(0,0x0f)

Slave Application

Here is a basic memory application from the 'demo' directory:

You need to add the following line to your verilog code, specifying the name of the program to run and the names of the verilog nets.

$scriptsim("slave.py", clk, control, address, data);

#
#   This is the memory model
#
# It implements a memory such that:
#   for writes, the write data is saved in memory
#     and later returned for a read
#   reading an uninitialized location returns 'x'
#

sim = scriptsim.Simulator()

# give names to the $scriptsim() arguments
clk, cmd, adr, data_in, data_out = sim.argv[1:]

# setup to do everything on the rising clock edge
clk.setup_event(scriptsim.RISING)

# lets make some defines
OP_IDLE, OP_WRITE, OP_READ, OP_DATA = range(4)

#
# initialize all outputs
#
data_out.v = 'z' # sets all data bits to 'z'

#
# set up a dictionary to hold memory contents
#
# This memory is infinite size and supports any
# address or data width (even vector sizes > 64 bits)
# Python implements this internally with hash tables
# and, if necessary, long integers
#
mem_dict = {}

#
# infinite loop reading and writing memory
#
print '\n This is the bus slave, slave.py\n'
while 1:
sim.resume_and_wait_for_event()

    # lets wait until resetting is done
    if sim.time() < 10:
        continue

    # verify cmd is not 'x'
    if cmd.x:
        print 'ERROR: at time',sim.time(),'cmd has unknown bits'
        data_out.v = 'z'
        continue

    # nothing to do for idle and DATA cycles
    # except tri-state data
    if cmd.n == OP_IDLE or cmd.n == OP_DATA:
        data_out.v = 'z'
        continue

    if adr.x:
        print 'ERROR: at time',sim.time(),'address has unknown bits'
    if cmd.n == OP_READ:
        if adr.x:
            data_out.v = 'x'
        else:
           # read from the memory
           # but if that location is uninitialized, return 'x'
            data_out.v = mem_dict.get(adr.n, '0')
           # you might want to change '0' to 'x' if memory is
           # not initialized to 0
    else: # OP_WRITE
        if data_in.x:
            print 'ERROR: at time',sim.time(),'data has unknown bits',data_in.
str
        else:
            if not adr.x:
           # simply save the write data in memory
           # so it can be retrieved later on a read
                mem_dict[adr.n] = data_in.n

Monitor Application

#
# This is a simple monitor program which outputs to the console
# It demonstrates how easily verilog nets can be accessed and printed
#

sim = scriptsim.Simulator()

# We need to access the following verilog nets
clk = sim.vvo("clock")
cmd = sim.vvo("op")
adr = sim.vvo("adr")
data = sim.vvo("data")

# setup to do everything on the rising clock edge
clk.setup_event(scriptsim.RISING)

# lets make some defines to make the code more readable
OP_IDLE, OP_WRITE, OP_READ, OP_DATA = range(4)

# for color highlighting, lets import the library
from ss_lib import * # import the scriptsim library functions

#
# infinite loop handling operations
#
while 1:
    sim.resume_and_wait_for_event() # wait for the next rising clock edge
    if cmd.x: # if the 'cmd' net has 'x' bits
        print "%8s %sCommand is 'x'%s" % (str(sim.time()),E_TAG,NO_TAG)
    elif cmd.n == OP_WRITE:
        print '%8s Write adr=%s data=%s' % (str(sim.time()), adr.h0, data.h0)
    elif cmd.n == OP_READ:
        read_time = sim.time()
    elif cmd.n == OP_DATA:
        print '%8s Read adr=%s data=%s' % (str(read_time), adr.h0, data.h0)

Demo.v - Verilog Demo of these 3 ScriptSim scripts

// basic demo which generates a clock
// and uses 3 ScriptSim programs to
// control the bus, act as memory, and monitor the bus

module Demo;
   wire clock;
   wire [1:0] op;
   wire [15:0] adr;
   wire [31:0] data;

   reg clock_reg;
   reg [1:0] op_reg;
   reg [15:0] adr_reg;
   reg [31:0] data_read;
   reg [31:0] data_write;

   assign clock = clock_reg;
   assign op = op_reg;
   assign adr = adr_reg;
   assign data = data_write;
   assign data = data_read;

   initial begin: main_block
      clock_reg = 1;
      $scriptsim("search.py");
      $scriptsim("monitor.py");
      $scriptsim("master.py", clock, op_reg, adr_reg, data_write);
      $scriptsim("slave.py",   clock, op, adr, data, data_read);
   end // block: main_block

   // generate a clock with 10ns period
   always begin: clock_gen
      #5 clock_reg = 1;
      #5 clock_reg = 0;
   end // block: clock_gen

endmodule // Demo

Resulting Display

Here is a real screen shot of the ScriptSim Tk console when running these 3 demo programs. The commands are generated by master.py, the memory is implemented by slave.py, and the prints to the console are generated by monitor.py.

console screen shot