#
#  Configuration and command file for a PCI master/target.
#
# Here we create a target by specifying the values (hardwired and writable)
#  of the configuration registers.
# If 2 numbers are present, the first specifies the 'hardwired capability'
#  and the second is effectively written to that register.
config deviceid=0x3323, vendorid=0x1023  # standard vendor and device ids'
config status=(0x20, 0x0)  # 66Mhz capable
config command=(0x7,0x4)   # has master,i/o,and memory. Enable master.
config base0=(0xffff0000, 0) # 64K of memory allowed by base register 0
config base1=(0xffffff01, 0) # 256 bytes of i/o allowed by base register 1
#
# Now we cause this agent to initiate cycles
# Note that for configuration commands, bits 15:11 of the address are decoded
# and end up driving idsel bits to the various agents
cmd=cr adr=0x000 data=0x33231023 # read vendorid, deviceid
cmd=cr adr=0x800 data=0x77777023 # read vendorid, deviceid
cmd=cr adr=0x2000 nodevsel        # no device will respond at this address
cmd=cr adr=0x004 data=0x200004   # read status, command
cmd=cr adr=0x804 data=0x200000   # read status, command

cmd=cw adr=0x010 data=0xffffffff # check base0 size
cmd=cr adr=0x010 data=0xffff0000
cmd=cw adr=0x010 data=0x00000000 # set memory to address 0
cmd=cw adr=0x014 data=0xffffffff # check base1 size
cmd=cr adr=0x014 data=0xffffff01
cmd=cw adr=0x014 data=0x00000000 # set io to address 0
cmd=cw adr=0x004 be=3 data=0x7   # enable memory, and io

cmd=cw adr=0x810 data=0xffffffff # check base0 size
cmd=cr adr=0x810 data=0xffff0000
cmd=cw adr=0x810 data=0x00010000 # set memory to address 0x10000
cmd=cw adr=0x814 data=0xffffffff # check base1 size
cmd=cr adr=0x814 data=0xffffff01
cmd=cw adr=0x814 data=0x00000100 # set io to address 0x100
cmd=cw adr=0x818 data=0xffffffff # check base2 size
cmd=cr adr=0x818 data=0x00000000 # doesn't have base2
cmd=cw adr=0x81c data=0xffffffff # check base3 size
cmd=cr adr=0x81c data=0x00000000 # doesn't have base3
cmd=cw adr=0x820 data=0xffffffff # check base4 size
cmd=cr adr=0x820 data=0x00000000 # doesn't have base4
cmd=cw adr=0x824 data=0xffffffff # check base5 size
cmd=cr adr=0x824 data=0x00000000 # doesn't have base5
cmd=cw adr=0x804 be=3 data=0x7   # enable scsi master, memory, and io
cmd=cr adr=0x804 be=3 data=0x200007   # verify
cmd=cw adr=0x1000 be=3 data=0x4  # enable lan as master

# verify simple i/o writes with byte enables
cmd=ir, adr=0x100, data=0
cmd=iw, adr=0x100, data=0xffffffff
cmd=ir, adr=0x100, data=0xffffffff
cmd=iw, adr=0x100, data=0x00000078, be=1
cmd=ir, adr=0x100, data=0xffffff78
cmd=iw, adr=0x100, data=0x00005600, be=2
cmd=ir, adr=0x100, data=0xffff5678
cmd=iw, adr=0x100, data=0x00340000, be=4
cmd=ir, adr=0x100, data=0xff345678
cmd=iw, adr=0x100, data=0x12000000, be=8
cmd=ir, adr=0x100, data=0x12345678

# verify simple memory writes with byte enables
cmd=mr, adr=0x10000, data=0
cmd=mw, adr=0x10000, data=0xffffffff
cmd=mr, adr=0x10000, data=0xffffffff
cmd=mw, adr=0x10000, data=0x00000078, be=1
cmd=mr, adr=0x10000, data=0xffffff78
cmd=mw, adr=0x10000, data=0x00005600, be=2
cmd=mr, adr=0x10000, data=0xffff5678
cmd=mw, adr=0x10000, data=0x00340000, be=4
cmd=mr, adr=0x10000, data=0xff345678
cmd=mw, adr=0x10000, data=0x12000000, be=8
cmd=mr, adr=0x10000, data=0x12345678

# verify 32-bit burst reads and writes (odd address)
cmd=mr adr=0x10004 data=(0*8)
cmd=mw adr=0x10004 data=(0xffffffff*8)
cmd=mr adr=0x10004 data=(0xffffffff*8)
cmd=mw adr=0x1000c data=(0x55555555*3)
cmd=mr adr=0x10000 data=0x12345678
cmd=mr adr=0x10004 data=(0xffffffff*2, 0x55555555*3, 0xffffffff*3, 0)

# verify 64-bit burst reads and writes (if pci64)
cmd=mr adr=0x10000 data=(0x12345678, 0xffffffff*2, 0x55555555*3, 0xffffffff*3, 0*2)
cmd=mw adr=0x10000 data=(0x77777777*3)
cmd=mw adr=0x10010 data=(0x66666666*4)
cmd=mr adr=0x10000 data=(0x77777777*3, 0x55555555, 0x66666666*4, 0xffffffff, 0*2)