Introduction to ScriptSim

In complex simulations, the verilog language does not have the power to meet all the verification requirements. As a result, vendors have developed proprietary languages, with expensive licensing, to extend verilog capabilities.

ScriptSim extends the verilog capabilities by using powerful, open source languages. Perl and Python are easy to learn, and the many perl and python modules make the languages incredibly powerful.

ScriptSim, like perl and python, is open source. No license server problems! No more waiting months for a simple fix because the vendor won't let you see the source code --- with open source you have the option of modifying the code yourself. Don't get locked into a proprietary product and language!

Almost all modern verilog simulators are compatible with ScriptSim. The simulator needs to support PLI version 1.0.

To use ScriptSim, add the verilog user function $scriptsim() to create script (perl or python) processes, and to communicate with existing processes.

To create a script process, add the following $scriptsim call to your verilog code:
$scriptsim("my_prog.py",id, ...);
The first parameter specifies the script pathname. The suffix tells ScriptSim if it is perl or python. This process is created, and all parameters are passed to the script. Parameters can be any verilog constants, registers, nets, etc. The 'id' is returned by the $scriptsim call and is used to make future calls to this script process.

Later calls to this process are done with the following verilog code:
$scriptsim(id, ...);
Again, parameters can be any verilog data types.

Then you have tremendous flexibility in your script. The script can run for a short time, or continue running for the entire simulation. The script can access any verilog registers or nets, and can sensitize to changes on registers or nets. For example, you may wish for your script to perform certain functions on the rising clock edge. You may use any perl or python modules, including those which create a GUI or perform IPC. ScriptSim supports both blocking and non-block I/O programming models.

A full PCI model is available with demonstrates most of the ScriptSim capability. The model is open source.

Some capabilities of ScriptSim which are not possible with verilog alone include searching the entire verilog design, finding and accessing the verilog source files, reading and writing (or forcing) any registers, nets, or variables anywhere in the design, and performing special operations when the simulation stops (at $stop) or when the simulation exits (at $finish).

Your perl and python code can wait for a period of time or wait for an event just as easily as with verilog. And your perl and python code can operate on verilog registers as if they were local perl or python variables - but with the advantages of flexible type conversions and unlimited vector sizes. ScriptSim seamlessly integrates these scripting languages with verilog.

ScriptSim doesn't limit you to some specific version of perl or python, or limit the extension modules you use. Any fairly recent version of perl or python is compatible with ScriptSim - including any extension modules you choose to use.

Both perl and python are equally well supported by ScriptSim and provide the same functionality in the simulation. The reason that both are supported is that it is almost impossible to convince a perl programmer to use python, or a python programmer to use perl. In a simulation you can have any mix of perl and python scripts.

Perl is the most popular language for scripting purposes. It has a huge following in the software community and the largest library of available extension modules. It was originally developed for smaller, text processing applications, but the ardent perl fanatic can do anything with this language.

Python is a simpler, easier to learn, more structured language which is more suitable for larger projects because it is easier to read and maintain than perl. It is weaker in the text processing area and stronger in the arithmetic processing than perl. A good simple tutorial for can be found at Instant Python.  The best source of information about Python including download information is available at  www.python.org  and they have an excellent tutorial at  www.python.org/doc/tut.

The Tk interface, initially developed for Tcl/Tk and adapted for use by other languages such as Perl and Python, allows a good windowed interface.  However, to use ScriptSim, no knowledge of Tk is required because ScriptSim builds a basic Tk display which is adequate for most applications.
 

Bus Monitors: For simple busses, viewing the verilog signal waveforms is adequate.  For today's split transaction busses, where multiple requests are generated and the responses return out-of-order, viewing the signal waveforms is tedious and unreliable.  The requests and responses must be decoded and formatted.  The responses must be correlated to the requests to form transactions.  The formatted requests and responses must be viewable in time order, or merged together and viewed in transaction order, and simply clicking on a request should highlight the response.  Bus protocol errors should be highlighted in color.  Statistics such as bus loading and throughput should be presented graphically.

ScriptSim provides the fastest way to implement a display for complex bus or system activity.  To verify an asic which connects 2 or more busses, your script could examine the busses and key internal signals in asics to generate a display which shows, at a system level, the functionality of the asic.