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The type_list is a list of strings indicating what is being searched for. The strings are from the verilog pli documentation, and include such items as accModule, accNet, accRegister, accIntegerVar, accRealVar, accTimeVar, accNamedEvent, etc. See the verilog documentation for the acc_next() command for further details of additional types of objects which can be searched for. The type_list strings can be abbreviated, upper or lower case, and the 'acc' prefix may be omitted. So 'accRegister' could also be specified as 'accregister', 'register', or 'reg'.
The list which is returned is a list of 5-element tuples. The first element of the tuple is the full name of the object. The second element is the acc_type, which is something like 'accModule', 'accNet', etc. The third element is the acc_fulltype, which in most cases is identical to the acc_type. The fourth element is the verilog source filename where this item is defined, and the fifth element is the line number in this verilog file. These 5 strings are obtained by the verilog pli calls acc_fetch_fullname(), acc_fetch_type(), acc_fetch_fulltype(), and acc_fetch_location().
Here are some examples:
# here is a recursive routine to descend the hierarchy looking
# at all the modules for the desired items
def search_recursive(module, search_list):
items_found = sim.find(module, search_list)
mod_list = sim.find(module, "accModule")
for i in mod_list:
items_found.append(search_sub_modules(i,
search_list))
return items_found
# lets use the routine to find all the nets and registers in the entire
design:
net_reg_list = search_recursive("/", ("net", "register"))
Once you have the name of an object, use the sim.new_arg() command to get a Sim_Parm type object. Then the value of the object can be read or written, and if desired, changes to the object can terminate a wait() command.